1. Field of the Invention
The present invention relates to a static RAM cell, and more particularly to a structure in which loads are connected with transistors forming a flip-flop as a storage element.
2. Description of the Prior Art
Referring to a conventional static RAM cell, a storage element is a flip-flop which is formed by two cross-connected inverters. It is necessary to greatly reduce a cell size of the storage element in the high density static RAM cell. FIGS. 4 and 5 show an electric circuit and a structure of the conventional high density static RAM cell which is manufactured by a MOS technology.
The static RAM cell comprises four N-channel bulk transistors and two high value polysilicon resistances. In FIGS. 4 and 5, access transistors Q1 and Q2 connect nodes A and B of a storage element cell with bit lines BL and BL, respectively.
A flip-flop FF includes transistors Q3 and Q4, and load resistances R1 and R2. The transistors Q1, Q2, Q3 and Q4 are formed as bulk elements on a semiconductor substrate by the MOS technology. To save space and make density high, the load resistances R1 and R2 are formed on a polysilicon layer which is deposited on the bulk elements.
As shown in FIG. 5, a P.sup.- -type silicon substrate is indicated at 50, an element isolation region is indicated at OX, a polysilicon gate electrode of the access transistor Q1 is indicated at 51, a polysilicon gate electrode of the transistor Q4 is indicated at 52, and a drain region of the transistor Q1 is indicated at 53.
FIG. 6 is a plan view showing the typical arrangement of a memory cell having the above-mentioned structure.
As shown in FIG. 6 (a), an active region 54 is formed, and a first polysilicon layer is then deposited and patterned. Consequently, the gates 51, 52 and 52' are formed. Prior to the deposition of the first polysilicon layer, connection windows 55 and 55' are provided on a gate oxide film of the drain regions 53 and 53'. Thus, the so-called buried connection can be obtained. Accordingly, the gate electrodes 52 and 52' are respectively extended over the drain regions of the N-channel bulk transistors Q1 and Q2 beyond the element isolation region OX by patterning the first polysilicon layer. Consequently, the gate electrodes 52 and 52' are directly connected with the drain regions 53 and 53'.
As shown in FIG. 6 (b), a second polysilicon layer is deposited on the gate electrodes 52 and 52' through an insulating film and is then patterned, so that the load resistances R1 and R2 are formed.
With the above-mentioned structure, the cell size is increased for the following reasons.
1. The buried connection is formed by the first polysilicon layer. Consequently, there is a minimum spacing, designated as Sgp in FIG. 5 and FIG. 6 (a), determined by photoetching resolution.
2. The buried connection needs a minimum overlap of the first polysilicon gate electrode to the drain regions, indicated as Lgd in FIG. 5.
The foregoing occurs depending on accuracy in a photolithographic process.
3. To obtain the buried connection, the connection windows are provided on the gate oxide film before the polysilicon is deposited. As a result, the gate oxide film is deteriorated.